The present invention relates to the field of static random access memory (SRAM) cells, and SRAM memory architecture providing for low ac power consumption.
FIG. 1 shows a SRAM memory array architecture of the prior art. This architecture utilizes a six transistor memory cell 200 as shown in FIG. 2. The six transistor SRAM bit cell 200 shown in FIG. 2 includes a first supply voltage, VDD 217, and a ground connection 218. The cell also includes a word line WLC. Bit lines BTC and BBC provide a connection to read and write data to the cell. The bit cell also includes a storage cell which includes four transistors, 206, 208, 210, 212, configured to store data. As is known in the art, transistors 206 and 208 act as load transistors and transistors 210 and 212 act as cross coupled storage transistors. As shown in the embodiment 200, the load transistors 206 and 208 are PMOS transistors, and 210 and 212 are NMOS transistors. Transistors 214 and 216 are word line, or row select, pass transistors.
In a static mode, when the cells in the memory array are not in write or read mode, bit lines BTC and BBC, shown in FIG. 2, are precharged to a VDD level. And the word line shown in FIG. 2 as WLC is at logic zero, which in most cases will be approximately ground. In this static state, a programmed cell can maintain the information equivalent to logic 0 or logic 1, since n-channel devices 214 and 216 are off, which isolates the storage cell that includes devices 206, 208, 210 and 212.
In a write mode, the WLC line which is coupled to a row of cells (e.g. N00, N01 . . . N0MM), as shown in FIG. 1, which contains the cell being written to is driven to logic 1 or VDD. To write to the cell to be programmed to store a binary 1, the bit line BTC for the cell being written to is driven to logic 0, and the bit line BBC is driven to logic 1. This results in the cell being programmed to logic 1, where the voltage at node 202 will be set at logic 1 and the voltage at node 204 will be set at logic 0 as is known in the art. To program the cell to logic 0 the bit line BTC is driven to logic 1 and the bit line BBC is driven to logic 0, such that 202 will be set at logic 0 and 204 will be set at logic 1 as is known in the art.
In the static mode, in between read and write operations, the bit lines BTC and BBC are held at a precharge voltage VDD using the PMOS transistors 102 of the precharge circuit 106. In the static mode the word line (WL0, WL1, . . . WLN) pass transistors shown in FIG. 2 (214 and 216) are held closed as the WLC voltage is at logic zero. To read the data from the cell the WLC voltage is changed to logic 1. The signal of voltage logic 1 on WLC is applied to the gates of the word line pass transistors 214, and 216, which opens the word line pass transistors 214 and 216, so that current can flow through the transistors. In addition to changing the WLC voltage being set to logic 1, the precharge circuit is closed so that the bit lines BTC and BBC are allowed to float. With the word line pass gate transistors open one of the bit lines BTC and BBC will discharge depending on which node 202 or 204 is at zero. For example if the cell is programmed at logic 1 then the BTC bit line will discharge through the NMOS transistor 214 and the cross coupled storage transistor 210, and BBC would remain floating at the VDD level. If the cell was programmed at logic 0 then BBC would discharge through 216 and 212, and BTC would remain at VDD. The switch (SW0, SW1 . . . SWM) connected to the cell which is being read will be closed and the sense circuitry 104 will read the difference in voltage in the bit lines BTC and BBC to determine whether the data is 1 (one) or 0 (zero).
In the prior art Static Random Access (SRAM) memory architecture 100 as shown in FIG. 1, there are three stages of operation. At stage 1 memory read/write operations require that all bit lines (BT0, BB0, BT1, BB1, . . . BTM, BBM) be precharged to logic 1 by the precharge circuitry 106, the precharge circuitry provides PMOS transistors 102, which in the static mode are opened by a PRCHG voltage signal 108 being at logic 0, which is applied to the gates of the PMOS transistors 102. Also all word lines (WLO, WL1, . . . WLN) are set to logic 0 before read read/write operation for any cell occurs.
At stage 2 of the memory read/write mode all are of the PMOS transistors 102 are closed (PRCHG voltage 108 is set to logic 1), so that the voltage on the bit lines is allowed to float, instead of being held at VDD. One of the word lines (e.g. WLO) is driven to logic 1. All the 6T (6-transistor)core memory cells (i.e. bit cells N00, N0 . . . N0M) coupled to this word line begin to discharge the bit lines (e.g. BT0, BB, BT1, BB1 . . . BTM, BBM). The discharge of the bit lines at this stage causes a large active AC power dissipation.
Stage 3 of the memory bit cell read/write operation is selecting one of the switches (SW0, SW1, . . . SWM) in the MUX block 103 by setting Y0, Y1 . . . or YM to logic 1. As shown in FIG. 1, Y0 is set selecting column 1. To write data to a bit cell at this stage requires using a write circuit 104 to program the selected individual bit cell, by applying a voltage differential to bit lines BT0 and BB0. (The write circuitry and sense circuitry is known to one of skill in the art, and shown as block 104 in FIG. 1.) To read data from the bit cell requires amplifying the differential signal between the bit lines BTC and BBC using a sense amplifier and then routing this to an output circuit.
Regardless of which mode is used, whether read or write, and what MUX switch will be closed, a bit line for each column of SRAM memory bit cells of the complete array will be discharged during every read/write operation before a new read/write cycle can begin, and the array has to precharged again. This is because the same PRCHG signal is applied to the gates of all of the PMOS transistors 102 of the precharge circuit 106, and all of the bit cells coupled to word line with logic 1 have word line pass transistors (e.g., 214 and 216) which are opened as a result of the word line generating a logic 1 signal.
One problem with this prior approach is that, for each read/write cycle, enough power to precharge and discharge all of the bit line pairs in the array is consumed, while all that is really needed is to program or read information for one bit line pair (e.g. BTC and BBC) during each read or write cycle. In the past, one technique employed to reduce the amount of AC power dissipated is to employ a multi bank architecture, that reduces the number of switches (SW) per sense amplifier block and so allows for selection of a particular bank of bit lines, corresponding to an array of bit cells, and thus only the array of bit cells corresponding to the selected bank of bit lines has to be precharged, thereby reducing the power required at the static stage. One issue with this approach is that it requires additional logic for determining with bank of bit lines to select and can requires additional sensing and write circuitry, and it still consumes enough power to precharge and discharge all bit line pairs in the selected bank.
The invention herein provides a system and method which allows for selecting and discharging only the bit lines that are coupled to the selected bit cell.
The present invention is directed to a static RAM bit cell and a system and method for operating an array of such static RAM bit cells. The static RAM bit cell of the present invention includes a storage cell configured to store data. It also includes a pair of word line pass transistors and a pair of column pass transistors coupled to the storage cell. The word line pass transistors are coupled to a word line such that they can be opened or closed in response to a signal on the word line. The column pass transistors are coupled to a column select transistor such that they can be opened and closed in response to a signal on the column select line. Using this configuration, signals can be generated on the word line and the column select line so that only a fraction of the total number of static RAM bit cells in an array need to be charged and discharged in connection with performing read and write operations to a specific static RAM bit cell.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized.